In recent years, significant progress has been made toward reductions in size, thickness, and weight of electronic apparatuses such as a portable telephone, a personal digital assistant, a liquid crystal display panel, and a notebook computer. Accordingly, a similar progress has been made toward reductions in size and weight and increase in performance and density with respect to various parts, which such apparatuses carry, such as a semiconductor device.
In the above situation, the semiconductor device currently realizes reduction in weight by use of a substrate in a film form, and further reduction in size and thickness by increase in density of semiconductor elements mounted on the substrate in the film form. The mounting method is called a COF (Chip on FPC) method.
Here, referring to FIGS. 6 through 9, a conventional semiconductor device by the above COF method is described as follows.
As shown in FIG. 6, the conventional semiconductor device includes a semiconductor element 18 and a wiring substrate 16. In the semiconductor element 18, a plurality of electrodes is formed. The electrode is provided with an aluminum pad 12 which is formed on the semiconductor element 18, and a bump electrode (Au bump) 13 which is formed on the aluminum pad 12. As shown in FIG. 7, a wiring substrate 16 is composed of a film substrate 14 on which a wiring pattern 15 is formed. The wiring pattern 15 is formed in the position corresponding to the Au bump 13. Also, the Au bump 13 and the wiring pattern 15 are connected to each other.
Here, referring to FIG. 8, a method for manufacturing the above semiconductor device is described below.
First, the semiconductor element 18 is aligned with respect to the wiring substrate 16. That is, the Au bump 13 is aligned so as to be at a predetermined position of the corresponding wiring pattern 15. Next, connection (joint) of the Au bump 13 and the wiring pattern 15 is made by thermo-compression bonding, by using a bonding tool 19. Then, the semiconductor element 18 and the wiring substrate 16 are sealed with a resin.
As described above, the thermo-compression bonding is currently a popular method of connecting the Au bump 13 and the wiring pattern 15 in the semiconductor device. However, in the thermo-compression bonding, a thermal stress is added to the film substrate 14 and the wiring pattern 15 in the wiring substrate 16. The thermal stress makes the film substrate 14 and the wiring pattern 15 to expand and contract (actually, they expand due to addition of heat) in accordance with respective coefficients of linear thermal expansion. At this point, since the film substrate 14 has a larger coefficient of linear thermal expansion than the wiring pattern 15, the film substrate 14 tries to make a larger expansion than the wiring pattern 15 does.
However, the wiring pattern 15 is formed on the film substrate 14, so that the wiring pattern 15 makes a larger expansion, following an expansion degree of the film substrate 14 (being pulled by the expansion of the film substrate 14). Conversely, the film substrate 14 makes a small expansion, following an expansion degree of the wiring pattern 15. That is, the stability of dimension of the wiring substrate 16 is not excellent because the wiring pattern 15 makes displacement, resulting in displacement with the Au bump 13. Therefore, this causes a problem of a deficiency of connection of the Au bump 13 and the wiring pattern 15.
Further, by change in temperature of the thermo-compression bonding, the displacement is corrected in accordance with a satisfactory dimension of the wiring substrate 16 of which dimension varies during manufacture so that the semiconductor element 18 and the wiring substrate 16 can be connected. However, in this case, it is necessary to change the temperature for each wiring substrate 16, thereby decreasing the efficiency in manufacture.
Further, as shown in FIG. 7, in the wiring substrate 16, a semiconductor element setting position 17 (a part surrounded by a dotted line), which is a position where the semiconductor element 18 (see FIG. 6) is set, has no wiring pattern other than a part where the Au bump 13 (see FIG. 6) is connected. That is, there is no wiring pattern in an inner part of the wiring pattern 15, and the film substrate 14 is bare. In the inner part of the wiring pattern 15, addition of a thermal stress makes the film substrate 14 to expand more than a part where the wiring pattern 15 is formed, thereby causing wrinkles. There is a problem that such a semiconductor device having wrinkles is judged as inferior goods by visual inspection. Further, another problem is that there is a possibility that the wrinkles gather moistures, and such moistures produce erosion in the vicinity of the Au bump 13, thereby causing a poor connection of the semiconductor element 18 and the wiring substrate 16.
In this regard, Japanese Unexamined Patent Application No. 2000-286309 (tokukai 2000-286309, published on Oct. 13, 2000) discloses a wiring substrate which prevents deformation (warping) by expansion and contraction caused by heat. As shown in FIG. 9, the wiring substrate 16 includes the bending wiring pattern 15 (having parts which extend in a first direction and second direction) formed on the film substrate 14. The bending wiring pattern supports the expansion of the film substrate 14 in a plurality of directions so as to reduce a warping by the expansion of the film substrate 14. Further, the above wiring substrate 16 is connected to the semiconductor element through inner leads (a part of the wiring pattern 15) 22, which is projected toward a device hole 21. Since a region where the wrinkles are made is the device hole 21, a poor connection therefore is not caused by wrinkles.
However, in the wiring substrate described in the Japanese Unexamined Patent Application No. 2000-286309, a bending wiring pattern is not formed in the vicinity of parts where the semiconductor element is connected. Due to a thermal stress, the wiring pattern 15 therefore cannot support the expansion of the film substrate 14 in a plurality of directions in the vicinity of parts where the semiconductor element is connected. This causes the expansion of the wiring substrate 16 (film substrate 14), thereby causing displacement of the inner leads 22. The displacement makes it impossible to ensure connection of the semiconductor element to the inner lead 22, resulting in a deficiency of connection (faulty electrical continuity).